It is often necessary in linear mixed-signal BiCMOS processes to mix low and high voltage components. Components selected for use in high voltage sections of a BiCMOS integrated circuit must have a high voltage capability or potential operating voltage. Bipolar devices are typically selected as the high voltage components due to their superior voltage handling ability in comparison to conventional MOS devices.
The voltage capability of a bipolar transistor is usually measured in terms of the open-base collector-emitter breakdown voltage, BVceo. The BVceo breakdown voltage is related to the current gain of a bipolar transistor through the following empirical relationship:
1.) BVceo=BVcbo(bulk)/(Hfe).sup.1/n PA0 BVcbo(bulk)=planar base-collector breakdown voltage at the bottom of the base-collector junction; PA0 Hfe=current gain of the transistor; and PA0 n=an empirical constant typically in the range of 3-6.
where:
The voltage capability of a bipolar transistor can be increased by increasing its BVceo breakdown voltage. A conventional technique for increasing BVceo breakdown voltage is to increase the thickness of the epitaxial layer in which the transistor is fabricated. Increasing the thickness of the epitaxial layer increases the BVcbo(bulk) breakdown voltage which, as seen from Equation 1 above, increases the BVceo breakdown voltage.
A drawback to the use of increased epitaxial layer thickness in an integrated circuit to increase voltage capability is the fact that all components in the integrated circuit, including any low-voltage bipolar transistors and CMOS devices, must be fabricated in the thicker epitaxial layer. In BiCMOS processes using a standard cell design approach based on devices characterized for an epitaxial layer of conventional thickness, increasing the thickness of the epitaxial layer is unacceptable. This is due to the fact that increasing epitaxial layer thickness requires scaling all devices to larger dimensions which in turn requires recharacterization or redesign of low-voltage cells already in the standard cell library.
For NPN transistors formed in an Nwell there is an additional drawback to the use of an epitaxial layer of increased thickness. In these NPN transistors, the Nwell must extend completely through a P epitaxial layer and contact a buried N+ collector layer. The additional drawback results from the fact that the formation of an N well that extends through the P epitaxial layer to the buried N+ collector layer becomes progressively more difficult with increasing thickness of the epitaxial layer.
Another conventional technique for increasing BVceo breakdown voltage for NPN transistors is to reduce the dopant concentration of the Nwell in which they are formed. Reduced dopant concentration results in an increase in the empirical constant n in equation 1 above which in turn results in an increase in BVceo breakdown voltage. A drawback to this technique is that many low voltage Nwell devices in the standard cell library cannot accept such a reduced dopant concentration. As a result, this technique requires additional process steps since separate implants must be performed for low voltage Nwell devices having a standard dopant concentration and for high voltage Nwell NPN transistors having a reduced dopant concentration.
A need therefore exists for a process that increases the voltage capability of a bipolar transistor without increasing the thickness of the epitaxial layer or requiring extra process steps.
Bipolar transistors having high current gain or Hfe are also required in certain BiCMOS processes. A conventional technique for increasing Hfe is to make the base width extremely narrow in order to increase integrated base charge. One drawback to this technique is that extremely narrow base widths are very difficult to precisely control. Consequently, the actual Hfe values for transistors fabricated using this technique cannot be very accurately predicted. Another drawback is that relatively low voltages will punch through such extremely narrow width base regions.
A need therefore exists for a process that increases the Hfe of a bipolar transistor without using extremely narrow base widths.